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Pakket: yosys-abc (0.52-2)

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Sequential Logic Synthesis and Verification Algorithms

ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.

This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.

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Pakket downloaden voor alle beschikbare platforms
Platform Pakketgrootte Geïnstalleerde grootte Bestanden
amd64 4.828,6 kB12.925,0 kB [overzicht]
arm64 4.271,9 kB12.054,0 kB [overzicht]
armel 4.084,7 kB11.854,0 kB [overzicht]
armhf 4.254,2 kB8.910,0 kB [overzicht]
i386 4.902,4 kB13.881,0 kB [overzicht]
ppc64el 4.906,7 kB15.382,0 kB [overzicht]
riscv64 4.798,1 kB10.774,0 kB [overzicht]