[ 原始碼： iverilog ]
套件：iverilog（10.2-1.1）
Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.
The compiler can target either simulation, or netlist (EDIF).
其他與 iverilog 有關的套件
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- dep: libbz2-1.0
- high-quality block-sorting file compressor library - runtime
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- dep: libc6 (>= 2.17)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
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- dep: libgcc1 (>= 1:3.0)
- GCC 支援函式庫
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- dep: libreadline7 (>= 6.0)
- GNU readline 與 history 函式庫，執行時期函式庫
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- dep: libstdc++6 (>= 5.2)
- GNU Standard C++ Library v3
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- dep: libtinfo6 (>= 6)
- shared low-level terminfo library for terminal handling
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- dep: zlib1g (>= 1:1.2.0)
- 壓縮函式庫 - 跑程式時用(runtime)
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- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer