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[ 源代码: iverilog  ]

软件包:iverilog(10.2-1.1)

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Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

标签: 领域: 电子学, 实做语言: C++, 用户接口: interface::commandline, role::program

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硬件架构 软件包大小 安装后大小 文件
arm64 1,611.1 kB6,024.0 kB [文件列表]