[ sid ]
[ experimental ]
[ Source: yosys ]
Package: yosys-abc (0.33-5 and others)
Links for yosys-abc
Debian Resources:
Download Source Package yosys:
- [yosys_0.33-5.dsc]
- [yosys_0.33.orig-abc.tar.gz]
- [yosys_0.33.orig.tar.gz]
- [yosys_0.33-5.debian.tar.xz]
Maintainers:
- Debian Science Maintainers (QA Page, Mail Archive)
- Ruben Undheim (QA Page)
- Sebastian Kuzminsky (QA Page)
- Daniel Gröber (QA Page)
External Resources:
- Homepage [github.com]
Similar packages:
Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.
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Download yosys-abc
| Architecture | Version | Package Size | Installed Size | Files |
|---|---|---|---|---|
| ppc64el | 0.33-5+b2 | 5,526.4 kB | 18,473.0 kB | [list of files] |