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Package: yosys-abc (0.52-2)

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Sekventiel logiksyntese og verifikationsalgoritmer

BC er et system til syntese og verifikation af binær sekventiel logikkredsløb, der optræder i synkrone udstyrsdesign. Systemet kombinerer skalerbar logisk optimering baseret på And-Inverter Graphs (AIG'er), optimal-delay DAG-baseret teknologikortlægning til opslagstabeller og standardceller samt innovative algoritmer til sekventiel syntese og verifikation.

Dette er en forgrening af berkeley-abc, der vedligeholdes af YosysHQ-holdet til brug i yosys RTL-synteseramme.

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Download yosys-abc

Download for all available architectures
Architecture Package Size Installed Size Files
alpha (unofficial port) 4,581.5 kB14,403.0 kB [list of files]
amd64 4,828.6 kB12,925.0 kB [list of files]
arm64 4,271.9 kB12,054.0 kB [list of files]
armel 4,084.7 kB11,854.0 kB [list of files]
armhf 4,254.2 kB8,910.0 kB [list of files]
i386 4,902.4 kB13,881.0 kB [list of files]
loong64 (unofficial port) 4,554.8 kB13,077.0 kB [list of files]
m68k (unofficial port) 4,525.7 kB13,240.0 kB [list of files]
mips64el 4,414.2 kB15,073.0 kB [list of files]
ppc64el 4,906.7 kB15,382.0 kB [list of files]
riscv64 4,798.1 kB10,774.0 kB [list of files]
sh4 (unofficial port) 5,338.4 kB11,506.0 kB [list of files]
x32 (unofficial port) 4,814.7 kB12,689.0 kB [list of files]