Пакет: myhdl-doc (0.11-1)

Hardware description generating framework (common documentation)

MyHDL turns Python into a hardware description and verification language, providing hardware engineers with the power of the Python ecosystem.

Python can then be used as an event-driven simulator using Python decorators actively to specify what corresponds to 'processes' in Verilog / VHDL and thereby achieve concurrency.

This is the common documentation package containing HTML pages and the man page.

Тази страница е налична и на следните езици (Настройване на езика по подразбиране):