Пакет: covered (0.7.10-3 и други)

Връзки за covered

Ресурси за Debian:

Изтегляне на пакет-източник covered.

Отговорници:

Външни препратки:

Начална страница [covered.sourceforge.net]

Подобни пакети:

Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Етикети: Field: Електроника, Implemented in: C, User Interface: interface::commandline, interface::graphical, X Window System, Role: Program, Interface Toolkit: uitoolkit::tk, use::viewing, X Window System: Application

Други пакети, свързани с covered

зависимости

препоръчани

предложени

enhances

dep: libc6 (>= 2.17)

GNU C Library: Shared libraries
също и виртуален пакет, предлаган от libc6-udeb
dep: libtcl8.6 (>= 8.6.0)

Tcl (the Tool Command Language) v8.6 - run-time library files
dep: libtk8.6 (>= 8.6.0)

Tk toolkit for Tcl and X11 v8.6 - run-time files
dep: tklib

standard Tk Library
dep: zlib1g (>= 1:1.1.4)

compression library - runtime

rec: iverilog

Icarus verilog compiler

или verilog

виртуален пакет, предлаган от iverilog

или gplcver (>= 2.12a-1.1)

Verilog simulator

Изтегляне на covered

Изтегляне за всички налични архитектури
Архитектура	Версия	Големина на пакета	Големина след инсталиране	Файлове
arm64	0.7.10-3+b1	433,3 кБ	2 254,0 кБ	[списък на файловете]