[ sid ]
[ 原始碼: yosys-plugin-ghdl ]
套件:yosys-plugin-ghdl(0.0~git20230419.5b64ccf-1)
yosys-plugin-ghdl 的相關連結
Debian 的資源:
下載原始碼套件 yosys-plugin-ghdl:
- [yosys-plugin-ghdl_0.0~git20230419.5b64ccf-1.dsc]
- [yosys-plugin-ghdl_0.0~git20230419.5b64ccf.orig.tar.gz]
- [yosys-plugin-ghdl_0.0~git20230419.5b64ccf-1.debian.tar.xz]
維護小組:
外部的資源:
- 主頁 [github.com]
相似套件:
VHDL to RTL synthesis plugin using GHDL
This yosys plugin allows running RTL synthesis from VHDL source code instead of yosys' native Verilog.
This allows a full synthesis flow from VHDL to hardware for FPGAs where the GHDL compiler is used to analyse the VHDL sources and yosys is used to perform logic optimization, technology mapping and convertion to netlist format.
其他與 yosys-plugin-ghdl 有關的套件
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- dep: libc6 (>= 2.14)
- GNU C 函式庫:共用函式庫
同時作為一個虛擬套件由這些套件填實: libc6-udeb
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- dep: libgcc-s1 (>= 3.3.1)
- GCC 支援函式庫
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- dep: libghdl-3-0-0 (>= 3.0.0+dfsg)
- VHDL compiler/simulator (shared library)
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- dep: libstdc++6 (>= 13.1)
- GNU Standard C++ Library v3