套件：covered（0.7.10-4） [debports]
Verilog code coverage analysis tool
Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.
其他與 covered 有關的套件
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- dep: libc6.1 (>= 2.34)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6.1-udeb
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- dep: libtcl8.6 (>= 8.6.0)
- Tcl (the Tool Command Language) v8.6 - run-time library files
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- dep: libtk8.6 (>= 8.6.0)
- Tk toolkit for Tcl and X11 v8.6 - run-time files
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- dep: tklib
- standard Tk Library
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- dep: zlib1g (>= 1:1.1.4)
- 壓縮函式庫 - 跑程式時用(runtime)