[ 原始碼： yosys ]
套件：yosys（0.8-1）
Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
其他與 yosys 有關的套件
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- dep: berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg)
- ABC - A System for Sequential Synthesis and Verification
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- dep: libc6 (>= 2.27)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
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- dep: libffi6 (>= 3.2)
- Foreign Function Interface library runtime
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- dep: libgcc1 (>= 1:3.0)
- GCC 支援函式庫
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- dep: libreadline7 (>= 6.0)
- GNU readline 與 history 函式庫，執行時期函式庫
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- dep: libstdc++6 (>= 5.2)
- GNU Standard C++ Library v3
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- dep: libtcl8.6 (>= 8.6.0)
- Tcl (the Tool Command Language) v8.6 - run-time library files
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- dep: python3
- interactive high-level object-oriented language (default python3 version)
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- dep: xdot
- interactive viewer for Graphviz dot files