[ 原始碼： qflow ]
套件：qflow（1.3.17+dfsg.1-2）
Open-Source Digital Synthesis Flow
This is a complete tool chain for synthesizing digital circuits starting from verilog source and ending in physical layout for a specific target fabrication process. In the world of commercial electronics, digital synthesis with a target application of a chip design is usually bundled into large EDA software systems. As commercial electronics designers need to maintain cutting-edge performance, these commercial toolchains get more and more expensive, and have largely priced themselves out of all but the established integrated circuit manufacturers. This leaves an unfortunate gap where startup companies and small businesses cannot afford to do any sort of integrated circuit design.
Qflow tries to fill this gap.
其他與 qflow 有關的套件
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- dep: berkeley-abc
- ABC - A System for Sequential Synthesis and Verification
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- dep: graywolf
- Placement for digital VLSI design
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- dep: libc6 (>= 2.29)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
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- dep: magic
- VLSI layout tool
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- dep: netgen-lvs
- Netlist comparison - Layout vs Schematic (LVS)
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- dep: opensta
- Gate-level Static Timing Analyzer
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- dep: python3
- interactive high-level object-oriented language (default python3 version)
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- dep: qrouter
- Multi-level, over-the-cell maze router
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- dep: tcl
- Tool Command Language (default version) - shell
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- dep: tcsh
- TENEX C Shell, an enhanced version of Berkeley csh
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- dep: yosys
- Framework for Verilog RTL synthesis
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- rec: python3-tk
- Tkinter - Writing Tk applications with Python 3.x
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- rec: qflow-tech-osu018 (= 1.3.17+dfsg.1-2)
- Technology files needed for qflow for osu018
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- rec: qflow-tech-osu035 (= 1.3.17+dfsg.1-2)
- Technology files needed for qflow for osu035
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- rec: qflow-tech-osu050 (= 1.3.17+dfsg.1-2)
- Technology files needed for qflow for osu050