[ sid ]
[ 源代码: yosys-plugin-ghdl ]
软件包:yosys-plugin-ghdl(0.0~git20230419.5b64ccf-1)
yosys-plugin-ghdl 的相关链接
Debian 的资源:
下载源码包 yosys-plugin-ghdl:
- [yosys-plugin-ghdl_0.0~git20230419.5b64ccf-1.dsc]
- [yosys-plugin-ghdl_0.0~git20230419.5b64ccf.orig.tar.gz]
- [yosys-plugin-ghdl_0.0~git20230419.5b64ccf-1.debian.tar.xz]
维护小组:
外部的资源:
- 主页 [github.com]
相似软件包:
VHDL to RTL synthesis plugin using GHDL
This yosys plugin allows running RTL synthesis from VHDL source code instead of yosys' native Verilog.
This allows a full synthesis flow from VHDL to hardware for FPGAs where the GHDL compiler is used to analyse the VHDL sources and yosys is used to perform logic optimization, technology mapping and convertion to netlist format.
其他与 yosys-plugin-ghdl 有关的软件包
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- dep: libc6 (>= 2.4)
- GNU C 语言运行库:共享库
同时作为一个虚包由这些包填实: libc6-udeb
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- dep: libgcc-s1 (>= 3.3.1)
- GCC 支持库
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- dep: libghdl-3-0-0 (>= 3.0.0+dfsg)
- VHDL compiler/simulator (shared library)
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- dep: libstdc++6 (>= 13.1)
- GNU 标准 C++ 库,第3版