Paket: opensta-dev (0~20191111gitc018cb2+dfsg-1) [debports]
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Externa resurser:
- Hemsida [github.com]
Liknande paket:
Gate-level Static Timing Analyzer - development files
After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.
It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.
This package contains the header files and some libraries for development.
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| Arkitektur | Paketstorlek | Installerad storlek | Filer |
|---|---|---|---|
| sparc64 (inofficiell anpassning) | 1.053,8 kbyte | 10.144,0 kbyte | [filförteckning] |