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[ Source: gplcver  ]

Package: gplcver (2.12a-4 and others)

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Verilog simulator

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.

Tags: Software Development: Need an extra tag, Interpreter, Field: Electronics, Implemented in: implemented-in::c, role::program, Purpose: Simulating

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Download gplcver

Download for all available architectures
Architecture Version Package Size Installed Size Files
alpha (unofficial port) 2.12a-4 804.2 kB2,269.0 kB [list of files]
amd64 2.12a-4 873.6 kB2,114.0 kB [list of files]
arm64 2.12a-4 804.4 kB2,205.0 kB [list of files]
armel 2.12a-4 759.4 kB1,944.0 kB [list of files]
armhf 2.12a-4 766.3 kB1,496.0 kB [list of files]
hppa (unofficial port) 2.12a-4 769.1 kB1,895.0 kB [list of files]
i386 2.12a-4 875.7 kB2,186.0 kB [list of files]
ia64 (unofficial port) 2.12a-2 999.5 kB3,859.0 kB [list of files]
loong64 (unofficial port) 2.12a-4 845.7 kB2,269.0 kB [list of files]
m68k (unofficial port) 2.12a-4 659.4 kB1,733.0 kB [list of files]
mips64el 2.12a-4 772.8 kB2,343.0 kB [list of files]
ppc64 (unofficial port) 2.12a-4 858.3 kB2,591.0 kB [list of files]
ppc64el 2.12a-4 874.6 kB2,461.0 kB [list of files]
riscv64 2.12a-4 859.9 kB1,805.0 kB [list of files]
s390x 2.12a-4 849.4 kB2,205.0 kB [list of files]
sh4 (unofficial port) 2.12a-4 798.9 kB1,558.0 kB [list of files]
sparc64 (unofficial port) 2.12a-4 743.7 kB2,341.0 kB [list of files]
x32 (unofficial port) 2.12a-4 814.9 kB1,867.0 kB [list of files]