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[ Source: gplcver  ]

Package: gplcver (2.12a-2 and others)

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Verilog simulator

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.

Tags: Software Development: Need an extra tag, Interpreter, Field: Electronics, Implemented in: implemented-in::c, role::program, Purpose: Simulating

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Download gplcver

Download for all available architectures
Architecture Version Package Size Installed Size Files
alpha (unofficial port) 2.12a-2 808.1 kB2,330.0 kB [list of files]
amd64 2.12a-2 819.6 kB1,935.0 kB [list of files]
arm64 2.12a-2 774.3 kB2,074.0 kB [list of files]
armel 2.12a-2 748.6 kB1,881.0 kB [list of files]
armhf 2.12a-2 756.5 kB1,453.0 kB [list of files]
hppa (unofficial port) 2.12a-2 755.2 kB1,912.0 kB [list of files]
i386 2.12a-2 864.5 kB2,155.0 kB [list of files]
ia64 (unofficial port) 2.12a-2 999.5 kB3,859.0 kB [list of files]
m68k (unofficial port) 2.12a-2 637.8 kB1,674.0 kB [list of files]
mips64el 2.12a-2 752.4 kB2,340.0 kB [list of files]
ppc64 (unofficial port) 2.12a-2 844.8 kB2,588.0 kB [list of files]
ppc64el 2.12a-2 857.9 kB2,458.0 kB [list of files]
riscv64 2.12a-2+b1 866.1 kB1,851.0 kB [list of files]
s390x 2.12a-2 767.3 kB2,138.0 kB [list of files]
sh4 (unofficial port) 2.12a-2 797.0 kB1,555.0 kB [list of files]
sparc64 (unofficial port) 2.12a-2 751.4 kB2,338.0 kB [list of files]
x32 (unofficial port) 2.12a-2 802.6 kB1,840.0 kB [list of files]