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[ Source: gplcver  ]

Package: gplcver (2.12a-1.1 and others)

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Verilog simulator

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.

Homepage: http://www.pragmatic-c.com/gpl-cver

Tags: Software Development: Need an extra tag, Interpreter, Field: Elektronika, Implemented in: implemented-in::c, role::program, Purpose: Simulating

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Download for all available architectures
Architecture Version Package Size Installed Size Files
ppc64el 2.12a-1.1+b2 724.1 kB2,139.0 kB [list of files]