Paketti: gplcver (2.12a-2)

Verilog simulator

Cver is a full 1995 IEEE P1364 standard Verilog simulator. It also implements some of the 2001 P1364 standard features. All three PLI interfaces (tf_, acc_, and vpi_) are implemented as defined in the IEEE 2001 P1364 LRM.

Tagit: Software Development: Need an extra tag, Interpreter, Field: Elektroniikka, Implemented in: implemented-in::c, role::program, Purpose: Simulating

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