Package: iverilog (11.0-1)

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Homepage [iverilog.icarus.com]

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Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

Tags: Field: Electronics, Implemented in: C++, User Interface: interface::commandline, role::program

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Download iverilog

Download for all available architectures
Architecture	Package Size	Installed Size	Files
amd64	1,962.2 kB	6,872.0 kB	[list of files]
arm64	1,754.2 kB	6,637.0 kB	[list of files]
armel	1,673.8 kB	5,847.0 kB	[list of files]
armhf	1,730.0 kB	4,616.0 kB	[list of files]
i386	2,060.6 kB	6,933.0 kB	[list of files]
mips64el	1,646.7 kB	8,235.0 kB	[list of files]
mipsel	1,669.5 kB	7,470.0 kB	[list of files]
ppc64el	1,948.8 kB	8,842.0 kB	[list of files]
s390x	1,777.3 kB	7,085.0 kB	[list of files]