Пакет: opensta-dev (0~20191111gitc018cb2+dfsg-1)

Gate-level Static Timing Analyzer - development files

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

This package contains the header files and some libraries for development.

Етикети: Software Development: Библиотеки, Role: Development Library

Тази страница е налична и на следните езици (Настройване на езика по подразбиране):